ddrinit: d56ea12
Ranks:                                                1
Die size:                                             0
Rank size:                                            13 MB
Full size:                                            13 MB
Full SDRAM Width:                                     0 bits
Primary SDRAM Width:                                  0 bits
ECC SDRAM Width:                                      0 bits
Device Width:                                         8 bits
Number of Row Addresses:                              65536
Number of Column Addresses:                           1024
Number of Bank Addresses:                             8
Bank Group Addressing:                                1
Clock Cycle Time (tCK):                               1250 ps
Minimum Clock Cycle Time (tCK min):                   0 ps
Maximum Clock Cycle Time (tCK max):                   0 ps
CAS# Latency Time (tAA min):                          25000 ps
Minimum Four Activate Windows Delay (tFAW):           40000 ps
RAS to CAS Delay Time (tRCD min):                     18750 ps
Row Precharge Delay Time (tRP min):                   18750 ps
Active to Precharge Delay Time (tRAS min):            42500 ps
Normal Refresh Recovery Delay Time (tRFC1 min):       0 ps
2x Mode Refresh Recovery Delay Time (tRFC2 min):      0 ps
4x Mode Refresh Recovery Delay Time (tRFC4 min):      0 ps
Short Row Active to Row Active Delay (tRRD_S min):    10000 ps
Long Row Active to Row Active Delay (tRRD_L min):     0 ps
Long CAS to CAS Delay Time (tCCD_L min):              0 ps
Minimum Active to Auto-Refresh Delay (tRC):           60000 ps

DDRMC0: Failed to initialize, time elapsed: 1385045 us: PHY training error
Ranks:                                                1
Die size:                                             0
Rank size:                                            13 MB
Full size:                                            13 MB
Full SDRAM Width:                                     0 bits
Primary SDRAM Width:                                  0 bits
ECC SDRAM Width:                                      0 bits
Device Width:                                         8 bits
Number of Row Addresses:                              65536
Number of Column Addresses:                           1024
Number of Bank Addresses:                             8
Bank Group Addressing:                                1
Clock Cycle Time (tCK):                               1250 ps
Minimum Clock Cycle Time (tCK min):                   0 ps
Maximum Clock Cycle Time (tCK max):                   0 ps
CAS# Latency Time (tAA min):                          25000 ps
Minimum Four Activate Windows Delay (tFAW):           40000 ps
RAS to CAS Delay Time (tRCD min):                     18750 ps
Row Precharge Delay Time (tRP min):                   18750 ps
Active to Precharge Delay Time (tRAS min):            42500 ps
Normal Refresh Recovery Delay Time (tRFC1 min):       0 ps
2x Mode Refresh Recovery Delay Time (tRFC2 min):      0 ps
4x Mode Refresh Recovery Delay Time (tRFC4 min):      0 ps
Short Row Active to Row Active Delay (tRRD_S min):    10000 ps
Long Row Active to Row Active Delay (tRRD_L min):     0 ps
Long CAS to CAS Delay Time (tCCD_L min):              0 ps
Minimum Active to Auto-Refresh Delay (tRC):           60000 ps

DDRMC1: Initialized successfully within 1404862 us, 1 ranks, speed 1600 MT/s
Failed to initialize DDR: Required DDRMCs have not been initialized